/**************************************************************************************************** * @file     FM33FR0XX.h
 *
 * @brief    CMSIS CORTEX-M0 Peripheral Access Layer Header File for
 *           FM33FR0XX from Keil.
 *
 * @version  V0.0.1
 * @date     24 october 2021
 *
 * @note     Generated with SVDConv V2.87e 
 *           from CMSIS SVD File 'FM33FR0XX.SVD' Version 1.0,
 *
 * @par      ARM Limited (ARM) is supplying this software for use with Cortex-M
 *           processor based microcontroller, but can be equally used for other
 *           suitable processor architectures. This file can be freely distributed.
 *           Modifications to this file shall be clearly marked.
 *
 *           THIS SOFTWARE IS PROVIDED “AS IS”. NO WARRANTIES, WHETHER EXPRESS, IMPLIED
 *           OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
 *           MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
 *           ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
 *           CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
 *
 *******************************************************************************************************/


/** @addtogroup Keil
  * @{
  */

/** @addtogroup FM33FR0XX
  * @{
  */

#ifndef FM33FR0XX_H
#define FM33FR0XX_H

#ifdef __cplusplus
extern "C" {
#endif

#define __RCHF_INITIAL_CLOCK        (8000000)        /* Value of the Internal RC HIGH oscillator in Hz */
#define __RCMF_CLOCK                (4000000)        /* Value of the Internal RC 4M oscillator in Hz */
#define __LPOSC_CLOCK               (32000)          /* Value of the Internal RC LOW oscillator in Hz */
#define __XTHF_CLOCK                (8000000)        /* Value of the EXTERNAL oscillator in Hz */
#define __XTLF_CLOCK                (32768)          /* Value of the EXTERNAL oscillator in Hz */


/* -------------------------  Interrupt Number Definition  ------------------------ */

typedef enum {

/* -------------------  FM33FR0XX Processor Exceptions Numbers  -------------------*/
  Reset_IRQn                    = -15,              /*!<   1  复位向量 */
  NMI_IRQn                      = -14,              /*!<   2  WKUPx中断
低功耗模式错误中断
存储器非法访问中断
Flash ECC检错中断 */
  HardFault_IRQn                = -13,              /*!<   3  HardFault中断向量 */
  SVC_IRQn                      = -5,               /*!<  11  SVCall系统服务请求 */
  PendSV_IRQn                   = -2,               /*!<  14  可挂起系统服务请求 */
  SysTick_IRQn                  = -1,               /*!<  15  内部定时器中断向量 */

/* --------------------  Cortex-M0 Specific Interrupt Numbers  --------------------*/
  WDT_IRQn                      = 0,                /*!<   0  窗口看门狗或独立看门狗中断 */
  SVD_IRQn                      = 1,                /*!<   1  电源监测报警中断 */
  RTC_IRQn                      = 2,                /*!<   2  实时时钟中断 */
  MUX0_IRQn                     = 3,                /*!<   3  可配置多路中断 */
  TSI_IRQn                      = 4,                /*!<   4  按键触摸检测中断 */
  ADC_IRQn                      = 5,                /*!<   5  ADC转换完成中断 */
  CAN0_IRQn                     = 6,                /*!<   6  CAN0中断 */
  MUX1_IRQn                     = 7,                /*!<   7  可配置多路中断 */
  MUX2_IRQn                     = 8,                /*!<   8  可配置多路中断 */
  MUX3_IRQn                     = 9,                /*!<   9  可配置多路中断 */
  MUX4_IRQn                     = 10,               /*!<  10  可配置多路中断 */
  MUX5_IRQn                     = 11,               /*!<  11  可配置多路中断 */
  MUX6_IRQn                     = 12,               /*!<  12  可配置多路中断 */
  MUX7_IRQn                     = 13,               /*!<  13  可配置多路中断 */
  MUX8_IRQn                     = 14,               /*!<  14  可配置多路中断 */
  I2CMX_IRQn                    = 15,               /*!<  15  I2C master中断 */
  LPUART1_IRQn                  = 16,               /*!<  16  LPUART1中断 */
  I2C_SMBX_IRQn                 = 17,               /*!<  17  I2C SMBUS中断 */
  MUX9_IRQn                     = 18,               /*!<  18  可配置多路中断 */
  AES_IRQn                      = 19,               /*!<  19  AES中断 */
  LPTIM_IRQn                    = 20,               /*!<  20  LPTIM16中断 */
  DMA_IRQn                      = 21,               /*!<  21  DMA中断 */
  WKUPX_IRQn                    = 22,               /*!<  22  WKUP引脚中断 */
  MUX10_IRQn                    = 23,               /*!<  23  可配置多路中断 */
  BSTIM_IRQn                    = 24,               /*!<  24  BSTIM16中断 */
  COMPX_IRQn                    = 25,               /*!<  25  COMPx中断 */
  MUX11_IRQn                    = 26,               /*!<  26  可配置多路中断 */
  MUX12_IRQn                    = 27,               /*!<  27  可配置多路中断 */
  ATIM_IRQn                     = 28,               /*!<  28  高级定时器中断 */
  MUX13_IRQn                    = 29,               /*!<  29  可配置多路中断 */
  GPIO_IRQn                     = 30,               /*!<  30  外部引脚中断 */
  ECCC_RAMP_FDET_IRQn           = 31,               /*!<  31  Flash ECC纠错中断/RAM奇偶校验错误中断/XTLF或XTHF停振检测中断 */
} IRQn_Type;


/** @addtogroup Configuration_of_CMSIS
  * @{
  */

/* ================================================================================ */
/* ================      Processor and Core Peripheral Section     ================ */
/* ================================================================================ */

/* ----------------Configuration of the CORTEX-M0 Processor and Core Peripherals---------------- */
#define __CM0_REV                 0x0100            /*!< CORTEX-M0 Core Revision                                               */
#define __MPU_PRESENT                  0            /*!< MPU present or not                                                    */
#define __VTOR_PRESENT                 1           /*!< VTOR present or not                                                    */
#define __NVIC_PRIO_BITS               2            /*!< Number of Bits used for Priority Levels                               */
#define __Vendor_SysTickConfig         0            /*!< Set to 1 if different SysTick Config is used                          */
/** @} */ /* End of group Configuration_of_CMSIS */

#include "core_cm0plus.h"                            /*!< Cortex-M0 processor and core peripherals */
#include "system_fm33fr0xx.h"                        /*!< FM33FR0XX System */

/* ================================================================================ */
/* ================       Device Specific Peripheral Section       ================ */
/* ================================================================================ */

/** @addtogroup Device_Peripheral_Registers
  * @{
  */

/* -------------------  Start of section using anonymous unions  ------------------ */
#if defined(__CC_ARM)
  #pragma push
  #pragma anon_unions
#elif defined(__ICCARM__)
  #pragma language=extended
#elif defined(__GNUC__)
/* anonymous unions are enabled by default */
#elif defined(__TMS470__)
/* anonymous unions are enabled by default */
#elif defined(__TASKING__)
  #pragma warning 586
#else
#warning Not supported compiler type
#endif


/* ================================================================================ */
/* ================                       FLASH                    ================ */
/* ================================================================================ */

typedef struct
{
  __IO uint32_t RDCR;                   /*!<  Flash Read Control Register,                          Address offset: 0x00 */
  __IO uint32_t RSV1;                   /*!<  RESERVED REGISTER,                                    Address offset: 0x04 */
  __I  uint32_t OPTBR;                  /*!<  Flash Option Bytes Register,                          Address offset: 0x08 */
  __IO uint32_t RSV2[2];                /*!<  RESERVED REGISTER,                                    Address offset: 0x0C */
  __IO uint32_t EPCR;                   /*!<  Flash Erase/Program Control Register,                 Address offset: 0x14 */
  __O  uint32_t KEY;                    /*!<  Flash Key Register,                                   Address offset: 0x18 */
  __IO uint32_t IER;                    /*!<  Flash Interrupt Enable Register,                      Address offset: 0x1C */
  __IO uint32_t ISR;                    /*!<  Flash Interrupt Status Register,                      Address offset: 0x20 */
  __IO uint32_t RSV3;                   /*!<  RESERVED REGISTER,                                    Address offset: 0x24 */
  __IO uint32_t ECCSR;                  /*!<  ,                                                     Address offset: 0x28 */
	__IO uint32_t RSV4[3];                /*!<  RESERVED REGISTER,                                    Address offset: 0x2C */
	__IO uint32_t ECCCR;                  /*!<  ,                                                     Address offset: 0x38 */
  __IO uint32_t RSV5[9];                /*!<  RESERVED REGISTER,                                    Address offset: 0x2C */
  __IO uint32_t ACLOCK1;                /*!<  Flash Application Code Lock Register1,                Address offset: 0x60 */
  __IO uint32_t ACLOCK2;                /*!<  Flash Application Code Lock Register1,                Address offset: 0x64 */
  __IO uint32_t ACLOCK3;                /*!<  Flash Application Code Lock Register1,                Address offset: 0x68 */
}FLASH_Type;


/* ================================================================================ */
/* ================                       PMU                      ================ */
/* ================================================================================ */

typedef struct
{
  __IO uint32_t CR;                     /*!<  Power Management Control Register,                    Address offset: 0x00 */
  __IO uint32_t WKTR;                   /*!<  Wakeup Time Register,                                 Address offset: 0x04 */
  __IO uint32_t WKFR;                   /*!<  Wakeup Source Flags Register,                         Address offset: 0x08 */
  __IO uint32_t IER;                    /*!<  PMU Interrupt Enable Register,                        Address offset: 0x0C */
  __IO uint32_t ISR;                    /*!<  PMU Interrupt and Status Register,                    Address offset: 0x10 */
  __IO uint32_t RSV1[10];               /*!<  RESERVED REGISTER,                                    Address offset: 0x14 */              
  __IO uint32_t BUFCR;                  /*!<  PMU Analog Buffer Control Register,                   Address offset: 0x3C */
  __IO uint32_t RSV2[4];                /*!<  RESERVED REGISTER,                                    Address offset: 0x40 */
  __IO uint32_t PTAT_CR;                /*!<  PMU PTAT Control Register,                            Address offset: 0x50 */
}PMU_Type;


/* ================================================================================ */
/* ================                      VREFP                     ================ */
/* ================================================================================ */

typedef struct
{
  __IO uint32_t CR;                     /*!<  PMU VREFP Control Register,                           Address offset: 0x00 */
  __IO uint32_t CFGR;                   /*!<  PMU VREFP Config Register,                            Address offset: 0x04 */
  __IO uint32_t RSV1;                   /*!<  RESERVED REGISTER,                                    Address offset: 0x08 */
  __IO uint32_t TR;                     /*!<  PMU VREFP Trim Register,                              Address offset: 0x0C */
}VREFP_Type;


/* ================================================================================ */
/* ================                       SCU                      ================ */
/* ================================================================================ */

typedef struct
{
  __I  uint32_t SYSCON;                 /*!<  Memory Capacity Query Register,                       Address offset: 0x00 */
  __IO uint32_t RSV1;                   /*!<  RESERVED REGISTER,                                    Address offset: 0x04 */
  __IO uint32_t HDFFLAG;                /*!<  Hardfault Query Register,                             Address offset: 0x08 */
}SCU_Type;


/* ================================================================================ */
/* ================                     INTMUX                     ================ */
/* ================================================================================ */

typedef struct
{
  __IO uint32_t CR;                     /*!<  Interrupt Multiplexer Control Register,               Address offset: 0x00 */
}INTMUX_Type;


/* ================================================================================ */
/* ================                       RMU                      ================ */
/* ================================================================================ */

typedef struct
{
  __IO uint32_t PDRCR;                  /*!<  ,                                                     Address offset: 0x00 */
  __IO uint32_t BORCR;                  /*!<  ,                                                     Address offset: 0x04 */
  __IO uint32_t LKPCR;                  /*!<  ,                                                     Address offset: 0x08 */
  __O  uint32_t SOFTRST;                /*!<  ,                                                     Address offset: 0x0C */
  __IO uint32_t RSTFR;                  /*!<  ,                                                     Address offset: 0x10 */
  __O  uint32_t PRSTEN;                 /*!<  ,                                                     Address offset: 0x14 */
  __IO uint32_t AHBRSTCR;                 /*!<  ,                                                     Address offset: 0x18 */
  __IO uint32_t APBRSTCR1;                /*!<  ,                                                     Address offset: 0x1C */
  __IO uint32_t APBRSTCR2;                /*!<  ,                                                     Address offset: 0x20 */
}RMU_Type;


/* ================================================================================ */
/* ================                      IWDT                      ================ */
/* ================================================================================ */

typedef struct
{
  __O  uint32_t SERV;                   /*!<  IWDT Service Register,                                Address offset: 0x00 */
  __IO uint32_t CR;                     /*!<  IWDT Config Register,                                 Address offset: 0x04 */
  __I  uint32_t CNT;                    /*!<  IWDT Counter Register,                                Address offset: 0x08 */
  __IO uint32_t WIN;                    /*!<  IWDT Window Register,                                 Address offset: 0x0C */
  __IO uint32_t IER;                    /*!<  IWDT Interrupt Enable Register,                       Address offset: 0x10 */
  __IO uint32_t ISR;                    /*!<  IWDT Interrupt Status Register,                       Address offset: 0x14 */
}IWDT_Type;


/* ================================================================================ */
/* ================                      WWDT                      ================ */
/* ================================================================================ */

typedef struct
{
  __O  uint32_t CR;                     /*!<  WWDT Control Register,                                Address offset: 0x00 */
  __IO uint32_t CFGR;                   /*!<  WWDT Config Register,                                 Address offset: 0x04 */
  __I  uint32_t CNT;                    /*!<  WWDT Counter Register,                                Address offset: 0x08 */
  __IO uint32_t IER;                    /*!<  WWDT Interrupt Enable Register,                       Address offset: 0x0C */
  __IO uint32_t ISR;                    /*!<  WWDT Interrupt Status Register,                       Address offset: 0x10 */
  __I  uint32_t PSC;                    /*!<  WWDT Prescaler Register,                              Address offset: 0x14 */
}WWDT_Type;


/* ================================================================================ */
/* ================                       CMU                      ================ */
/* ================================================================================ */

typedef struct
{
  __IO uint32_t SYSCLKCR;               /*!<  System Clock Control Register,                        Address offset: 0x00 */
  __IO uint32_t RCHFCR;                 /*!<  RCHF Control Register,                                Address offset: 0x04 */
  __IO uint32_t RCHFTR;                 /*!<  RCHF Trim Register,                                   Address offset: 0x08 */
  __IO uint32_t PLLCR;                  /*!<  PLL Control Register,                                 Address offset: 0x0C */
  __IO uint32_t RCLPCR;                 /*!<  RCLP Control Register,                                Address offset: 0x10 */
  __IO uint32_t RCLPTR;                 /*!<  RCLP Trim Register,                                   Address offset: 0x14 */
  __IO uint32_t XTLFCR;                 /*!<  XTLF Control Register,                                Address offset: 0x18 */
  __IO uint32_t LSCLKSEL;               /*!<  LSCLK Select Register,                                Address offset: 0x1C */
  __IO uint32_t XTHFCR;                 /*!<  XTHF Control Register,                                Address offset: 0x20 */
  __IO uint32_t RSV1[2];                /*!<  RESERVED REGISTER,                                    Address offset: 0x24 */
  __IO uint32_t IER;                    /*!<  Interrupt Enable Register,                            Address offset: 0x2C */
  __IO uint32_t ISR;                    /*!<  Interrupt Status Register,                            Address offset: 0x30 */
  __IO uint32_t PCLKCR1;                /*!<  Peripheral bus Clock Control Register1,               Address offset: 0x34 */
  __IO uint32_t PCLKCR2;                /*!<  Peripheral bus Clock Control Register2,               Address offset: 0x38 */
  __IO uint32_t PCLKCR3;                /*!<  Peripheral bus Clock Control Register3,               Address offset: 0x3C */
  __IO uint32_t PCLKCR4;                /*!<  Peripheral bus Clock Control Register4,               Address offset: 0x40 */
  __IO uint32_t OPCCR1;                 /*!<  Peripheral Clock Config Register1,                    Address offset: 0x44 */
  __IO uint32_t OPCCR2;                 /*!<  Peripheral Clock Config Register 2,                   Address offset: 0x48 */
  __IO uint32_t OPCCR3;                 /*!<   Peripheral Clock Config Register 3,                  Address offset: 0x4C */
  __IO uint32_t AHBMCR;                 /*!<  AHB Master Control Register,                          Address offset: 0x50 */
  __IO uint32_t CCCR;                   /*!<  Clock Calibration Control Register,                   Address offset: 0x54 */
  __IO uint32_t CCFR;                   /*!<  Clock Calibration Config Register,                    Address offset: 0x58 */
  __I  uint32_t CCNR;                   /*!<  Clock Calibration Counter Register,                   Address offset: 0x5C */
  __IO uint32_t CCISR;                  /*!<  Clock Calibration Interrupt Status Register,          Address offset: 0x60 */
}CMU_Type;


/* ================================================================================ */
/* ================                       SVD                      ================ */
/* ================================================================================ */

typedef struct
{
  __IO uint32_t CFGR;                   /*!<  SVD Config Register,                                  Address offset: 0x00 */
  __IO uint32_t CR;                     /*!<  SVD Control Register,                                 Address offset: 0x04 */
  __IO uint32_t IER;                    /*!<  SVD Interrupt Enable Register,                        Address offset: 0x08 */
  __IO uint32_t ISR;                    /*!<  SVD Interrupt Status Register,                        Address offset: 0x0C */
  __IO uint32_t VSR;                    /*!<  SVD reference Voltage Select Register,                Address offset: 0x10 */
}SVD_Type;


/* ================================================================================ */
/* ================                       AES                      ================ */
/* ================================================================================ */

typedef struct
{
  __IO uint32_t CR;                     /*!<  AES Control Register,                                 Address offset: 0x00 */
  __IO uint32_t IER;                    /*!<  AES Interrupt Enable Register,                        Address offset: 0x04 */
  __IO uint32_t ISR;                    /*!<  AES Interrupt Status Register,                        Address offset: 0x08 */
  __IO uint32_t DIR;                    /*!<  AES Data Input Register,                              Address offset: 0x0C */
  __I  uint32_t DOR;                    /*!<  AES Data Output Register,                             Address offset: 0x10 */
  __IO uint32_t KEY0;                   /*!<  AES Key Register 0,                                   Address offset: 0x14 */
  __IO uint32_t KEY1;                   /*!<  AES Key Register 1,                                   Address offset: 0x18 */
  __IO uint32_t KEY2;                   /*!<  AES Key Register 2,                                   Address offset: 0x1C */
  __IO uint32_t KEY3;                   /*!<  AES Key Register 3,                                   Address offset: 0x20 */
  __IO uint32_t KEY4;                   /*!<  AES Key Register 4,                                   Address offset: 0x24 */
  __IO uint32_t KEY5;                   /*!<  AES Key Register 5,                                   Address offset: 0x28 */
  __IO uint32_t KEY6;                   /*!<  AES Key Register 6,                                   Address offset: 0x2C */
  __IO uint32_t KEY7;                   /*!<  AES Key Register 7,                                   Address offset: 0x30 */
  __IO uint32_t IVR0;                   /*!<  AES Initial Vector Register 0,                        Address offset: 0x34 */
  __IO uint32_t IVR1;                   /*!<  AES Initial Vector Register 1,                        Address offset: 0x38 */
  __IO uint32_t IVR2;                   /*!<  AES Initial Vector Register 2,                        Address offset: 0x3C */
  __IO uint32_t IVR3;                   /*!<  AES Initial Vector Register 3,                        Address offset: 0x40 */
  __IO uint32_t H0;                     /*!<  AES MultH parameter Register 0,                       Address offset: 0x44 */
  __IO uint32_t H1;                     /*!<  AES MultH parameter Register 1,                       Address offset: 0x48 */
  __IO uint32_t H2;                     /*!<  AES MultH parameter Register 2,                       Address offset: 0x4C */
  __IO uint32_t H3;                     /*!<  AES MultH parameter Register 3,                       Address offset: 0x50 */
}AES_Type;


/* ================================================================================ */
/* ================                       RNG                      ================ */
/* ================================================================================ */

typedef struct
{
  __IO uint32_t CR;                     /*!<  ,                                                     Address offset: 0x00 */
  __I  uint32_t DOR;                    /*!<  ,                                                     Address offset: 0x04 */
  __IO uint32_t RSV1[2];                /*!<  RESERVED REGISTER,                                    Address offset: 0x08 */
  __IO uint32_t SR;                     /*!<  ,                                                     Address offset: 0x10 */
  __IO uint32_t CRCCR;                  /*!<  ,                                                     Address offset: 0x14 */
  __IO uint32_t CRCDIR;                 /*!<  ,                                                     Address offset: 0x18 */
  __IO uint32_t CRCSR;                  /*!<  ,                                                     Address offset: 0x1C */
}RNG_Type;


/* ================================================================================ */
/* ================                      COMP                      ================ */
/* ================================================================================ */

typedef struct
{
  __IO uint32_t CR;              /*!< ComparatorControl Register 1,                        Address offset: 0x00 */

} COMP_Type;

typedef struct
{
  __IO uint32_t ICR;                    /*!<  Comparator Interrupt Config Register,                 Address offset: 0x0C */
  __IO uint32_t ISR;                    /*!<  Comparator Interrupt Status Register,                 Address offset: 0x10 */
  __IO uint32_t BUFCR;                  /*!<  Comparator Buffer Control Register,                   Address offset: 0x14 */
}COMP_COMMON_Type;


/* ================================================================================ */
/* ================                      DIVAS                      ================ */
/* ================================================================================ */

typedef struct
{
  __IO uint32_t END;                    /*!<  ,                                                     Address offset: 0x00 */
  __IO uint32_t SOR;                    /*!<  ,                                                     Address offset: 0x04 */
  __I  uint32_t QUOT;                   /*!<  ,                                                     Address offset: 0x08 */
  __I  uint32_t REMD;                   /*!<  ,                                                     Address offset: 0x0C */
  __I  uint32_t SR;                     /*!<  ,                                                     Address offset: 0x10 */
}DIVAS_Type;


/* ================================================================================ */
/* ================                     I2CSMBx                    ================ */
/* ================================================================================ */

typedef struct
{
  __IO uint32_t CR1;                    /*!<  I2C SMBus Control Register,                           Address offset: 0x00 */
  __IO uint32_t CR2;                    /*!<  I2C SMBus Control Register,                           Address offset: 0x04 */
  __IO uint32_t IER;                    /*!<  I2C SMBus Intterupt Enable Register,                  Address offset: 0x08 */
  __IO uint32_t ISR;                    /*!<  I2C Master Interrupt Status Register,                 Address offset: 0x0C */
  __IO uint32_t BGR;                    /*!<  ,                                                     Address offset: 0x10 */
  __IO uint32_t TCR;                    /*!<  ,                                                     Address offset: 0x14 */
  __IO uint32_t TOR;                    /*!<  ,                                                     Address offset: 0x18 */
  __I  uint32_t RXBUF;                   /*!<  ,                                                     Address offset: 0x1C */
  __IO uint32_t TXBUF;                   /*!<  ,                                                     Address offset: 0x20 */
  __IO uint32_t SADR;                   /*!<  ,                                                     Address offset: 0x24 */
  __I  uint32_t CRC_DR;                 /*!<  ,                                                     Address offset: 0x28 */
  __IO uint32_t CRC_LFSR;               /*!<  ,                                                     Address offset: 0x2C */
  __IO uint32_t CRC_POLY;               /*!<  ,                                                     Address offset: 0x30 */
}I2CSMB_Type;


/* ================================================================================ */
/* ================                      I2Cx                      ================ */
/* ================================================================================ */

typedef struct
{
  __IO uint32_t MSPCFGR;                /*!<  I2C Master Config Register,                           Address offset: 0x00 */
  __IO uint32_t MSPCR;                  /*!<  I2C Master Control Register,                          Address offset: 0x04 */
  __IO uint32_t MSPIER;                 /*!<  I2C Master Intterupt Enable Register,                 Address offset: 0x08 */
  __IO uint32_t MSPISR;                 /*!<  I2C Master Interrupt Status Register,                 Address offset: 0x0C */
  __IO uint32_t MSPSR;                  /*!<  I2C Master Status Register,                           Address offset: 0x10 */
  __IO uint32_t MSPBGR;                 /*!<  I2C Master Baud rate Generator Register,              Address offset: 0x14 */
  __IO uint32_t MSPBUF;                 /*!<  I2C Master transfer Buffer,                           Address offset: 0x18 */
  __IO uint32_t MSPTCR;                 /*!<  I2C Master Timing Control Register,                   Address offset: 0x1C */
  __IO uint32_t MSPTOR;                 /*!<  I2C Master Time-Out Register,                         Address offset: 0x20 */
}I2C_Type;


/* ================================================================================ */
/* ================                      UART                      ================ */
/* ================================================================================ */

typedef struct
{
  __IO uint32_t IRCR;                   /*!<  Infrared modulation Control Register,                 Address offset: 0x00 */
}UART_COMMON_Type;


/* ================================================================================ */
/* ================                      UARTx                     ================ */
/* ================================================================================ */

typedef struct
{
  __IO uint32_t CSR;                    /*!<  UARTx Control Status Register,                        Address offset: 0x00 */
  __IO uint32_t IER;                    /*!<  UARTx Interrupt Enable Register,                      Address offset: 0x04 */
  __IO uint32_t ISR;                    /*!<  UARTx Interrupt Status Register,                      Address offset: 0x08 */
  __IO uint32_t TODR;                   /*!<  UARTx Time-Out and Delay Register,                    Address offset: 0x0C */
  __I  uint32_t RXBUF;                  /*!<  UARTx Receive Buffer,                                 Address offset: 0x10 */
  __O  uint32_t TXBUF;                  /*!<  UARTx Transmit Buffer,                                Address offset: 0x14 */
  __IO uint32_t BGR;                    /*!<  UARTx Baud rate Generator Register,                   Address offset: 0x18 */
  __IO uint32_t RSV1;                   /*!<  RESERVED REGISTER,                                    Address offset: 0x1C */
  __IO uint32_t MCR;                    /*!<  UARTx Mode Control Register,                          Address offset: 0x20 */
  __IO uint32_t LINCR;                  /*!<  UARTx LIN Control Register,                           Address offset: 0x24 */
  __I  uint32_t LINBSR;                 /*!<  UARTx LIN Baud Sync Register,                         Address offset: 0x28 */
  __IO uint32_t RSV2[5];                /*!<  RESERVED REGISTER,                                    Address offset: 0x2C */
  __IO uint32_t SCISR;                  /*!<  UARTx Smart Card Interrupt Status Register,           Address offset: 0x40 */
  __IO uint32_t SCIER;                  /*!<  UARTx Smart Card Interrupt Enable Register,           Address offset: 0x44 */
  __IO uint32_t FFCR;                   /*!<  UARTx Smart Card Frame Format Control Register,       Address offset: 0x48 */
  __IO uint32_t EGTR;                   /*!<  UARTx Smart Card Extra Guard Time Register,           Address offset: 0x4C */
  __IO uint32_t CODR;                   /*!<  UARTx Smart Card Clock Output Register,               Address offset: 0x50 */
}UART_Type;


/* ================================================================================ */
/* ================                     LPUARTx                    ================ */
/* ================================================================================ */

typedef struct
{
  __IO uint32_t CSR;                    /*!<  LPUARTx Control Status Register,                      Address offset: 0x00 */
  __IO uint32_t IER;                    /*!<  LPUARTx Interrupt Enable Register,                    Address offset: 0x04 */
  __IO uint32_t ISR;                    /*!<  LPUARTx Interrupt Status Register,                    Address offset: 0x08 */
  __IO uint32_t BMR;                    /*!<  LPUARTx Baud rate Modulation Register,                Address offset: 0x0C */
  __I  uint32_t RXBUF;                  /*!<  LPUARTx Receive Buffer Register,                      Address offset: 0x10 */
  __IO uint32_t TXBUF;                  /*!<  LPUARTx Transmit Buffer Register,                     Address offset: 0x14 */
  __IO uint32_t DMR;                    /*!<  LPUARTx data Matching Register,                       Address offset: 0x18 */
}LPUART_Type;


/* ================================================================================ */
/* ================                      SPIx                      ================ */
/* ================================================================================ */

typedef struct
{
  __IO uint32_t CR1;                    /*!<  SPIx Control Register1,                               Address offset: 0x00 */
  __IO uint32_t CR2;                    /*!<  SPIx Control Register2,                               Address offset: 0x04 */
  __IO uint32_t CR3;                    /*!<  SPIx Control Register3,                               Address offset: 0x08 */
  __IO uint32_t IER;                    /*!<  SPIx Interrupt Enable Register,                       Address offset: 0x0C */
  __IO uint32_t ISR;                    /*!<  SPIx Status Register,                                 Address offset: 0x10 */
  __O  uint32_t TXBUF;                  /*!<  SPIx Transmit Buffer,                                 Address offset: 0x14 */
  __I  uint32_t RXBUF;                  /*!<  SPIx Receive Buffer,                                  Address offset: 0x18 */
  __IO uint32_t RSV1;                   /*!<  RESERVED REGISTER,                                    Address offset: 0x1C */
  __IO uint32_t I2SCR;                  /*!<  SPIx I2S Control Register,                            Address offset: 0x20 */
  __IO uint32_t I2SPR;                  /*!<  SPIx I2S Prescaler Register,                          Address offset: 0x24 */
}SPI_Type;


/* ================================================================================ */
/* ================                      CANx                      ================ */
/* ================================================================================ */

typedef struct
{
  __IO uint32_t CR;                     /*!<  CANx Control Register,                                Address offset: 0x00 */
  __IO uint32_t MSR;                    /*!<  CANx mode select register,                            Address offset: 0x04 */
  __IO uint32_t BRPR;                   /*!<  CANx Baud rate Prescaler Register,                    Address offset: 0x08 */
  __IO uint32_t BTR;                    /*!<  CANx Bit Timing Register,                             Address offset: 0x0C */
  __I  uint32_t ECR;                    /*!<  CANx Error Counter Register,                          Address offset: 0x10 */
  __IO uint32_t ESR;                    /*!<  CANx Error Status Register,                           Address offset: 0x14 */
  __I  uint32_t SR;                     /*!<  CANx Status Register,                                 Address offset: 0x18 */
  __IO uint32_t RX_ISR;                 /*!<  CANx Interrupt Status Register,                       Address offset: 0x1C */
  __IO uint32_t RX_IER;                 /*!<  CANx Interrupt Enable Register,                       Address offset: 0x20 */
  __IO uint32_t RSV1;                   /*!<  RESERVED REGISTER,                                    Address offset: 0x24 */
  __IO uint32_t TXB_CR;                 /*!<  CANx Transmit Buffer Control Register,                Address offset: 0x28 */
  __IO uint32_t TXB_SR;                 /*!<   Transmit Buffer Status Register,                     Address offset: 0x2C */
  __O  uint32_t TXB0_IDR;               /*!<  CANx Transmit Buffer 0 ID Register,                   Address offset: 0x30 */
  __O  uint32_t TXB0_DLCR;              /*!<  CANx Transmit Buffer 0 DLC Register,                  Address offset: 0x34 */
  __O  uint32_t TXB0_DW1R;              /*!<  CANx Transmit Buffer 0 DataWord1 Register,            Address offset: 0x38 */
  __O  uint32_t TXB0_DW2R;              /*!<  CANx Transmit Buffer 0 DataWord2 Register,            Address offset: 0x3C */
  __O  uint32_t TXB1_IDR;               /*!<  CANx Transmit Buffer 1 ID Register,                   Address offset: 0x40 */
  __O  uint32_t TXB1_DLCR;              /*!<  CANx Transmit Buffer 1 DLC Register,                  Address offset: 0x44 */
  __O  uint32_t TXB1_DW1R;              /*!<  CANx Transmit Buffer 1 DataWord1 Register,            Address offset: 0x48 */
  __O  uint32_t TXB1_DW2R;              /*!<  CANx Transmit Buffer 1 DataWord2 Register,            Address offset: 0x4C */
  __O  uint32_t TXB2_IDR;               /*!<  CANx Transmit Buffer 2 ID Register,                   Address offset: 0x50 */
  __O  uint32_t TXB2_DLCR;              /*!<  CANx Transmit Buffer 2 DLC Register,                  Address offset: 0x54 */
  __O  uint32_t TXB2_DW1R;              /*!<  CANx Transmit Buffer 2 DataWord1 Register,            Address offset: 0x58 */
  __O  uint32_t TXB2_DW2R;              /*!<  CANx Transmit Buffer 2 DataWord2 Register,            Address offset: 0x5C */
  __IO uint32_t AFR;                    /*!<  Acceptance Filter Register,                           Address offset: 0x60 */
  __IO uint32_t AFMR1;                  /*!<  Acceptance Filter Mask Register1,                     Address offset: 0x64 */
  __IO uint32_t AFIR1;                  /*!<  Acceptance Filter ID Register1,                       Address offset: 0x68 */
  __IO uint32_t AFMR2;                  /*!<  Acceptance Filter Mask Register2,                     Address offset: 0x6C */
  __IO uint32_t AFIR2;                  /*!<  Acceptance Filter ID Register2,                       Address offset: 0x70 */
  __IO uint32_t AFMR3;                  /*!<  Acceptance Filter Mask Register3,                     Address offset: 0x74 */
  __IO uint32_t AFIR3;                  /*!<  Acceptance Filter ID Register3,                       Address offset: 0x78 */
  __IO uint32_t AFMR4;                  /*!<  Acceptance Filter Mask Register4,                     Address offset: 0x7C */
  __IO uint32_t AFIR4;                  /*!<  Acceptance Filter ID Register4,                       Address offset: 0x80 */
  __IO uint32_t RSV2[31];               /*!<  RESERVED REGISTER,                                    Address offset: 0x84 */
  __O  uint32_t RXF_IDR;                /*!<  CANx RX FIFO ID Register,                             Address offset: 0x100 */
  __O  uint32_t RXF_DLCR;               /*!<  CANx RX FIFO DLC Register,                            Address offset: 0x104 */
  __O  uint32_t RXF_DW1R;               /*!<  CANx RX FIFO Data Word1 Register,                     Address offset: 0x108 */
  __O  uint32_t RXF_DW2R;               /*!<  CANx RX FIFO Data Word2 Register,                     Address offset: 0x10C */
}CAN_Type;


/* ================================================================================ */
/* ================                       DMA                      ================ */
/* ================================================================================ */

typedef struct
{
  __IO uint32_t GCR;                    /*!<  DMA Global Control Register,                          Address offset: 0x00 */
  __IO uint32_t CH0CR;                  /*!<  Channel 0 Control Register,                           Address offset: 0x04 */
  __IO uint32_t CH0MAR;                 /*!<  Channel 0 Memory Address Register,                    Address offset: 0x08 */
  __IO uint32_t CH1CR;                  /*!<  Channel 1 Control Register,                           Address offset: 0x0C */
  __IO uint32_t CH1MAR;                 /*!<  Channel 1 Memory Address Register,                    Address offset: 0x10 */
  __IO uint32_t CH2CR;                  /*!<  Channel 2 Control Register,                           Address offset: 0x14 */
  __IO uint32_t CH2MAR;                 /*!<  Channel 2 Memory Address Register,                    Address offset: 0x18 */
  __IO uint32_t CH3CR;                  /*!<  Channel 3 Control Register,                           Address offset: 0x1C */
  __IO uint32_t CH3MAR;                 /*!<  Channel 3 Memory Address Register,                    Address offset: 0x20 */
  __IO uint32_t CH4CR;                  /*!<  Channel 4 Control Register,                           Address offset: 0x24 */
  __IO uint32_t CH4MAR;                 /*!<  Channel 4 Memory Address Register,                    Address offset: 0x28 */
  __IO uint32_t CH5CR;                  /*!<  Channel 5 Control Register,                           Address offset: 0x2C */
  __IO uint32_t CH5MAR;                 /*!<  Channel 5 Memory Address Register,                    Address offset: 0x30 */
  __IO uint32_t CH6CR;                  /*!<  Channel 6 Control Register,                           Address offset: 0x34 */
  __IO uint32_t CH6MAR;                 /*!<  Channel 6 Memory Address Register,                    Address offset: 0x38 */
  __IO uint32_t CH7CR;                  /*!<  Channel 11 Control Register,                          Address offset: 0x3C */
  __IO uint32_t CH7FLSAD;               /*!<  Channel 11 Flash Address Register,                    Address offset: 0x40 */
  __IO uint32_t CH7RAMAD;               /*!<  Channel 11 RAM Address Register,                      Address offset: 0x44 */
  __IO uint32_t ISR;                    /*!<  DMA Interrupt Status Register,                        Address offset: 0x48 */
  __IO uint32_t RSV1[7];                /*!<  RESERVED REGISTER,                                    Address offset: 0x4C */
  __IO uint32_t TSI_CR;                 /*!<  DMA TSI Control Register,                             Address offset: 0x68 */
  __IO uint32_t TSI0_MAR;               /*!<  DMA TSI Channle0 Memory Address Register,             Address offset: 0x6C */
  __IO uint32_t TSI1_MAR;               /*!<  DMA TSI Channle1 Memory Address Register,             Address offset: 0x70 */
  __IO uint32_t TSI2_MAR;               /*!<  DMA TSI Channle2 Memory Address Register,             Address offset: 0x74 */
  __IO uint32_t TSI3_MAR;               /*!<  DMA TSI Channle3 Memory Address Register,             Address offset: 0x78 */
  __IO uint32_t TSI4_MAR;               /*!<  DMA TSI Channle4 Memory Address Register,             Address offset: 0x7C */
  __IO uint32_t TSI5_MAR;               /*!<  DMA TSI Channle5 Memory Address Register,             Address offset: 0x80 */
  __IO uint32_t TSI6_MAR;               /*!<  DMA TSI Channle6 Memory Address Register,             Address offset: 0x84 */
  __IO uint32_t TSI7_MAR;               /*!<  DMA TSI Channle7 Memory Address Register,             Address offset: 0x88 */
  __IO uint32_t TSI8_MAR;               /*!<  DMA TSI Channle8 Memory Address Register,             Address offset: 0x8C */
  __IO uint32_t TSI9_MAR;               /*!<  DMA TSI Channle9 Memory Address Register,             Address offset: 0x90 */
  __IO uint32_t TSI10_MAR;              /*!<  DMA TSI Channle10 Memory Address Register,            Address offset: 0x94 */
  __IO uint32_t TSI11_MAR;              /*!<  DMA TSI Channle11 Memory Address Register,            Address offset: 0x98 */
  __IO uint32_t TSI12_MAR;              /*!<  DMA TSI Channle12 Memory Address Register,            Address offset: 0x9C */
  __IO uint32_t TSI13_MAR;              /*!<  DMA TSI Channle13 Memory Address Register,            Address offset: 0xA0 */
  __IO uint32_t TSIPROX_MAR;            /*!<  DMA TSI Channle Prox Memory Address Register,         Address offset: 0xA4 */
}DMA_Type;


/* ================================================================================ */
/* ================                       CRC                      ================ */
/* ================================================================================ */

typedef struct
{
  __IO uint32_t DR;                     /*!<  CRC Data Register,                                    Address offset: 0x00 */
  __IO uint32_t CR;                     /*!<  CRC Control Register,                                 Address offset: 0x04 */
  __IO uint32_t LFSR;                   /*!<  CRC Linear Feedback Shift Register,                   Address offset: 0x08 */
  __IO uint32_t XOR;                    /*!<  CRC output XOR Register,                              Address offset: 0x0C */
  __IO uint32_t RSV1[3];                /*!<  RESERVED REGISTER,                                    Address offset: 0x10 */
  __IO uint32_t POLY;                   /*!<  CRC Polynominal Register,                             Address offset: 0x1C */
}CRC_Type;


/* ================================================================================ */
/* ================                      ATIM                      ================ */
/* ================================================================================ */

typedef struct
{
  __IO uint32_t CR1;                    /*!<  ,                                                     Address offset: 0x00 */
  __IO uint32_t CR2;                    /*!<  ,                                                     Address offset: 0x04 */
  __IO uint32_t SMCR;                   /*!<  ,                                                     Address offset: 0x08 */
  __IO uint32_t DIER;                   /*!<  ,                                                     Address offset: 0x0C */
  __IO uint32_t ISR;                    /*!<  ,                                                     Address offset: 0x10 */
  __O  uint32_t EGR;                    /*!<  ,                                                     Address offset: 0x14 */
  __IO uint32_t CCMR1;                  /*!<  ,                                                     Address offset: 0x18 */
  __IO uint32_t CCMR2;                  /*!<  ,                                                     Address offset: 0x1C */
  __IO uint32_t CCER;                   /*!<  ,                                                     Address offset: 0x20 */
  __IO uint32_t CNT;                    /*!<  ,                                                     Address offset: 0x24 */
  __IO uint32_t PSC;                    /*!<  ,                                                     Address offset: 0x28 */
  __IO uint32_t ARR;                    /*!<  ,                                                     Address offset: 0x2C */
  __IO uint32_t RCR;                    /*!<  ,                                                     Address offset: 0x30 */
  __IO uint32_t CCR1;                   /*!<  ,                                                     Address offset: 0x34 */
  __IO uint32_t CCR2;                   /*!<  ,                                                     Address offset: 0x38 */
  __IO uint32_t CCR3;                   /*!<  ,                                                     Address offset: 0x3C */
  __IO uint32_t CCR4;                   /*!<  ,                                                     Address offset: 0x40 */
  __IO uint32_t BDTR;                   /*!<  ,                                                     Address offset: 0x44 */
  __IO uint32_t DCR;                    /*!<  ,                                                     Address offset: 0x48 */
  __IO uint32_t DMAR;                   /*!<  ,                                                     Address offset: 0x4C */
  __IO uint32_t RSV1[4];                /*!<  RESERVED REGISTER,                                    Address offset: 0x50 */
  __IO uint32_t BKCR;                   /*!<  ,                                                     Address offset: 0x60 */
}ATIM_Type;


/* ================================================================================ */
/* ================                      TAU                       ================ */
/* ================================================================================ */

typedef struct
{
  __IO uint32_t TAU0CR;                 /*!<  ,                                                     Address offset: 0x00 */
  __IO uint32_t TAU1CR;                 /*!<  ,                                                     Address offset: 0x04 */
}TAU_COMMON_Type;


/* ================================================================================ */
/* ================                      TAU0                      ================ */
/* ================================================================================ */

typedef struct
{
  __IO uint32_t T0CFGR;                 /*!<  ,                                                     Address offset: 0x10 */
  __IO uint32_t T1CFGR;                 /*!<  ,                                                     Address offset: 0x14 */
  __IO uint32_t T2CFGR;                 /*!<  ,                                                     Address offset: 0x18 */
  __IO uint32_t T3CFGR;                 /*!<  ,                                                     Address offset: 0x1C */
  __IO uint32_t T4CFGR;                 /*!<  ,                                                     Address offset: 0x20 */
  __IO uint32_t T5CFGR;                 /*!<  ,                                                     Address offset: 0x24 */
  __IO uint32_t T6CFGR;                 /*!<  ,                                                     Address offset: 0x28 */
  __IO uint32_t T7CFGR;                 /*!<  ,                                                     Address offset: 0x2C */
  __IO uint32_t T0MDR;                  /*!<  ,                                                     Address offset: 0x30 */
  __IO uint32_t T1MDR;                  /*!<  ,                                                     Address offset: 0x34 */
  __IO uint32_t T2MDR;                  /*!<  ,                                                     Address offset: 0x38 */
  __IO uint32_t T3MDR;                  /*!<  ,                                                     Address offset: 0x3C */
  __IO uint32_t T4MDR;                  /*!<  ,                                                     Address offset: 0x40 */
  __IO uint32_t T5MDR;                  /*!<  ,                                                     Address offset: 0x44 */
  __IO uint32_t T6MDR;                  /*!<  ,                                                     Address offset: 0x48 */
  __IO uint32_t T7MDR;                  /*!<  ,                                                     Address offset: 0x4C */
  __IO uint32_t T0ARR;                  /*!<  ,                                                     Address offset: 0x50 */
  __IO uint32_t T1ARR;                  /*!<  ,                                                     Address offset: 0x54 */
  __IO uint32_t T2ARR;                  /*!<  ,                                                     Address offset: 0x58 */
  __IO uint32_t T3ARR;                  /*!<  ,                                                     Address offset: 0x5C */
  __IO uint32_t T4ARR;                  /*!<  ,                                                     Address offset: 0x60 */
  __IO uint32_t T5ARR;                  /*!<  ,                                                     Address offset: 0x64 */
  __IO uint32_t T6ARR;                  /*!<  ,                                                     Address offset: 0x68 */
  __IO uint32_t T7ARR;                  /*!<  ,                                                     Address offset: 0x6C */
  __IO uint32_t T0CCR;                  /*!<  ,                                                     Address offset: 0x70 */
  __IO uint32_t T1CCR;                  /*!<  ,                                                     Address offset: 0x74 */
  __IO uint32_t T2CCR;                  /*!<  ,                                                     Address offset: 0x78 */
  __IO uint32_t T3CCR;                  /*!<  ,                                                     Address offset: 0x7C */
  __IO uint32_t T4CCR;                  /*!<  ,                                                     Address offset: 0x80 */
  __IO uint32_t T5CCR;                  /*!<  ,                                                     Address offset: 0x84 */
  __IO uint32_t T6CCR;                  /*!<  ,                                                     Address offset: 0x88 */
  __IO uint32_t T7CCR;                  /*!<  ,                                                     Address offset: 0x8C */
  __IO uint32_t T0IER;                  /*!<  ,                                                     Address offset: 0x90 */
  __IO uint32_t T1IER;                  /*!<  ,                                                     Address offset: 0x94 */
  __IO uint32_t T2IER;                  /*!<  ,                                                     Address offset: 0x98 */
  __IO uint32_t T3IER;                  /*!<  ,                                                     Address offset: 0x9C */
  __IO uint32_t T4IER;                  /*!<  ,                                                     Address offset: 0xA0 */
  __IO uint32_t T5IER;                  /*!<  ,                                                     Address offset: 0xA4 */
  __IO uint32_t T6IER;                  /*!<  ,                                                     Address offset: 0xA8 */
  __IO uint32_t T7IER;                  /*!<  ,                                                     Address offset: 0xAC */
  __IO uint32_t T0ISR;                  /*!<  ,                                                     Address offset: 0xB0 */
  __IO uint32_t T1ISR;                  /*!<  ,                                                     Address offset: 0xB4 */
  __IO uint32_t T2ISR;                  /*!<  ,                                                     Address offset: 0xB8 */
  __IO uint32_t T3ISR;                  /*!<  ,                                                     Address offset: 0xBC */
  __IO uint32_t T4ISR;                  /*!<  ,                                                     Address offset: 0xC0 */
  __IO uint32_t T5ISR;                  /*!<  ,                                                     Address offset: 0xC4 */
  __IO uint32_t T6ISR;                  /*!<  ,                                                     Address offset: 0xC8 */
  __IO uint32_t T7ISR;                  /*!<  ,                                                     Address offset: 0xCC */
  __I  uint32_t T0CNTR;                 /*!<  ,                                                     Address offset: 0xD0 */
  __I  uint32_t T1CNTR;                 /*!<  ,                                                     Address offset: 0xD4 */
  __I  uint32_t T2CNTR;                 /*!<  ,                                                     Address offset: 0xD8 */
  __I  uint32_t T3CNTR;                 /*!<  ,                                                     Address offset: 0xDC */
  __I  uint32_t T4CNTR;                 /*!<  ,                                                     Address offset: 0xE0 */
  __I  uint32_t T5CNTR;                 /*!<  ,                                                     Address offset: 0xE4 */
  __I  uint32_t T6CNTR;                 /*!<  ,                                                     Address offset: 0xE8 */
  __I  uint32_t T7CNTR;                 /*!<  ,                                                     Address offset: 0xEC */
}TAU0_Type;


/* ================================================================================ */
/* ================                      TAU1                      ================ */
/* ================================================================================ */

typedef struct
{
  __IO uint32_t T0CFGR;                 /*!<  ,                                                     Address offset: 0xF0 */
  __IO uint32_t T1CFGR;                 /*!<  ,                                                     Address offset: 0xF4 */
  __IO uint32_t T2CFGR;                 /*!<  ,                                                     Address offset: 0xF8 */
  __IO uint32_t T3CFGR;                 /*!<  ,                                                     Address offset: 0xFC */
  __IO uint32_t T0MDR;                  /*!<  ,                                                     Address offset: 0x100 */
  __IO uint32_t T1MDR;                  /*!<  ,                                                     Address offset: 0x104 */
  __IO uint32_t T2MDR;                  /*!<  ,                                                     Address offset: 0x108 */
  __IO uint32_t T3MDR;                  /*!<  ,                                                     Address offset: 0x10C */
  __IO uint32_t T0ARR;                  /*!<  ,                                                     Address offset: 0x110 */
  __IO uint32_t T1ARR;                  /*!<  ,                                                     Address offset: 0x114 */
  __IO uint32_t T2ARR;                  /*!<  ,                                                     Address offset: 0x118 */
  __IO uint32_t T3ARR;                  /*!<  ,                                                     Address offset: 0x11C */
  __IO uint32_t T0CCR;                  /*!<  ,                                                     Address offset: 0x120 */
  __IO uint32_t T1CCR;                  /*!<  ,                                                     Address offset: 0x124 */
  __IO uint32_t T2CCR;                  /*!<  ,                                                     Address offset: 0x128 */
  __IO uint32_t T3CCR;                  /*!<  ,                                                     Address offset: 0x12C */
  __IO uint32_t T0IER;                  /*!<  ,                                                     Address offset: 0x130 */
  __IO uint32_t T1IER;                  /*!<  ,                                                     Address offset: 0x134 */
  __IO uint32_t T2IER;                  /*!<  ,                                                     Address offset: 0x138 */
  __IO uint32_t T3IER;                  /*!<  ,                                                     Address offset: 0x13C */
  __IO uint32_t T0ISR;                  /*!<  ,                                                     Address offset: 0x140 */
  __IO uint32_t T1ISR;                  /*!<  ,                                                     Address offset: 0x144 */
  __IO uint32_t T2ISR;                  /*!<  ,                                                     Address offset: 0x148 */
  __IO uint32_t T3ISR;                  /*!<  ,                                                     Address offset: 0x14C */
  __I  uint32_t T0CNTR;                 /*!<  ,                                                     Address offset: 0x150 */
  __I  uint32_t T1CNTR;                 /*!<  ,                                                     Address offset: 0x154 */
  __I  uint32_t T2CNTR;                 /*!<  ,                                                     Address offset: 0x158 */
  __I  uint32_t T3CNTR;                 /*!<  ,                                                     Address offset: 0x15C */
}TAU1_Type;


/* ================================================================================ */
/* ================                     BSTIM16                    ================ */
/* ================================================================================ */

typedef struct
{
  __IO uint32_t CR1;                    /*!<  BSTIM16 Control Register1,                            Address offset: 0x00 */
  __IO uint32_t CR2;                    /*!<  BSTIM16 Control Register2,                            Address offset: 0x04 */
  __IO uint32_t RSV1;                   /*!<  RESERVED REGISTER,                                    Address offset: 0x08 */
  __IO uint32_t IER;                    /*!<  BSTIM16 Interrupt Enable Register,                    Address offset: 0x0C */
  __IO uint32_t ISR;                    /*!<  BSTIM16 Interrupt Status Register,                    Address offset: 0x10 */
  __O  uint32_t EGR;                    /*!<  BSTIM16 Event Generation Register,                    Address offset: 0x14 */
  __IO uint32_t RSV2[3];                /*!<  RESERVED REGISTER,                                    Address offset: 0x18 */
  __IO uint32_t CNT;                    /*!<  BSTIM16 Counter Register,                             Address offset: 0x24 */
  __IO uint32_t PSC;                    /*!<  BSTIM16 Prescaler Register,                           Address offset: 0x28 */
  __IO uint32_t ARR;                    /*!<  BSTIM16 Auto-Reload Register,                         Address offset: 0x2C */
}BSTIM16_Type;


/* ================================================================================ */
/* ================                     LPTIM16                    ================ */
/* ================================================================================ */

typedef struct
{
  __IO uint32_t CFGR;                   /*!<  LPTIM16 Config Register,                              Address offset: 0x00 */
  __I  uint32_t CNT;                    /*!<  LPTIM16 Counter Register,                             Address offset: 0x04 */
  __IO uint32_t CCSR;                   /*!<  LPTIM16 Capture/Compare Control and Status Register,  Address offset: 0x08 */
  __IO uint32_t ARR;                    /*!<  LPTIM16 Auto-Reload Register,                         Address offset: 0x0C */
  __IO uint32_t IER;                    /*!<  LPTIM16 Interrupt Enable Register,                    Address offset: 0x10 */
  __IO uint32_t ISR;                    /*!<  LPTIM16 Interrupt Status Register,                    Address offset: 0x14 */
  __IO uint32_t CR;                     /*!<  LPTIM16 Control Register,                             Address offset: 0x18 */
  __IO uint32_t RSV1;                   /*!<  RESERVED REGISTER,                                    Address offset: 0x1C */
  __IO uint32_t CCR1;                   /*!<  LPTIM16 Capture/Compare Register1,                    Address offset: 0x20 */
  __IO uint32_t CCR2;                   /*!<  LPTIM16 Capture/Compare Register2,                    Address offset: 0x24 */
}LPTIM16_Type;


/* ================================================================================ */
/* ================                       RTC                      ================ */
/* ================================================================================ */

typedef struct
{
  __IO uint32_t WER;                    /*!<  RTC Write Enable Register,                            Address offset: 0x00 */
  __IO uint32_t IER;                    /*!<  RTC Interrupt Enable Register,                        Address offset: 0x04 */
  __IO uint32_t ISR;                    /*!<  RTC Interrupt Status Register,                        Address offset: 0x08 */
  __IO uint32_t BCDSEC;                 /*!<  BCD format time second registers,                     Address offset: 0x0C */
  __IO uint32_t BCDMIN;                 /*!<  BCD format time minute registers,                     Address offset: 0x10 */
  __IO uint32_t BCDHOUR;                /*!<  BCD format time hour registers,                       Address offset: 0x14 */
  __IO uint32_t BCDDAY;                 /*!<  BCD format time day registers,                        Address offset: 0x18 */
  __IO uint32_t BCDWEEK;                /*!<  BCD format time week registers,                       Address offset: 0x1C */
  __IO uint32_t BCDMONTH;               /*!<  BCD format time month registers,                      Address offset: 0x20 */
  __IO uint32_t BCDYEAR;                /*!<  BCD format time year registers,                       Address offset: 0x24 */
  __IO uint32_t ALARM;                  /*!<  RTC Alarm Register,                                   Address offset: 0x28 */
  __IO uint32_t TMSEL;                  /*!<  RTC Time Mark Select,                                 Address offset: 0x2C */
  __IO uint32_t ADJUST;                 /*!<  RTC time Adjust Register,                             Address offset: 0x30 */
  __IO uint32_t ADSIGN;                 /*!<   time Adjust Sign Register,                           Address offset: 0x34 */
  __IO uint32_t RSV1;                   /*!<  RESERVED REGISTER,                                    Address offset: 0x38 */
  __IO uint32_t SBSCNT;                 /*!<  RTC Sub-Second Counter,                               Address offset: 0x3C */
  __IO uint32_t CR;                     /*!<  RTC Control Register,                                 Address offset: 0x40 */
}RTC_Type;


/* ================================================================================ */
/* ================                       LCD                      ================ */
/* ================================================================================ */

typedef struct
{
  __IO uint32_t CR;                     /*!<  ,                                                     Address offset: 0x00 */
  __IO uint32_t TEST;                   /*!<  ,                                                     Address offset: 0x04 */
  __IO uint32_t FCR;                    /*!<  ,                                                     Address offset: 0x08 */
  __IO uint32_t FLKT;                   /*!<  ,                                                     Address offset: 0x0C */
  __IO uint32_t RSV1;                   /*!<  RESERVED REGISTER,                                    Address offset: 0x10 */
  __IO uint32_t IER;                    /*!<  ,                                                     Address offset: 0x14 */
  __IO uint32_t ISR;                    /*!<  ,                                                     Address offset: 0x18 */
  __IO uint32_t RSV2[2];                /*!<  RESERVED REGISTER,                                    Address offset: 0x1C */
  __IO uint32_t DATA0;                  /*!<  ,                                                     Address offset: 0x24 */
  __IO uint32_t DATA1;                  /*!<  ,                                                     Address offset: 0x28 */
  __IO uint32_t DATA2;                  /*!<  ,                                                     Address offset: 0x2C */
  __IO uint32_t DATA3;                  /*!<  ,                                                     Address offset: 0x30 */
  __IO uint32_t DATA4;                  /*!<  ,                                                     Address offset: 0x34 */
  __IO uint32_t DATA5;                  /*!<  ,                                                     Address offset: 0x38 */
  __IO uint32_t DATA6;                  /*!<  ,                                                     Address offset: 0x3C */
  __IO uint32_t DATA7;                  /*!<  ,                                                     Address offset: 0x40 */
  __IO uint32_t DATA8;                  /*!<  ,                                                     Address offset: 0x44 */
  __IO uint32_t DATA9;                  /*!<  ,                                                     Address offset: 0x48 */
  __IO uint32_t DATA10;                 /*!<  ,                                                     Address offset: 0x4C */
  __IO uint32_t COMEN;                  /*!<  ,                                                     Address offset: 0x50 */
  __IO uint32_t SEGEN0;                 /*!<  ,                                                     Address offset: 0x54 */
  __IO uint32_t SEGEN1;                 /*!<  ,                                                     Address offset: 0x58 */
}LCD_Type;


/* ================================================================================ */
/* ================                       ADC                      ================ */
/* ================================================================================ */

typedef struct
{
  __IO uint32_t ISR;                    /*!<  ADC Interrupt and Status Register,                    Address offset: 0x00 */
  __IO uint32_t IER;                    /*!<  ADC Interrupt Enable Register,                        Address offset: 0x04 */
  __IO uint32_t CR1;                    /*!<  ADC Control Register1,                                Address offset: 0x08 */
  __IO uint32_t CR2;                    /*!<  ADC Control Register2,                                Address offset: 0x0C */
  __IO uint32_t CALR;                   /*!<  ADC Calibration Register,                             Address offset: 0x10 */
  __IO uint32_t CFGR1;                  /*!<  ADC Config Register1,                                 Address offset: 0x14 */
  __IO uint32_t CFGR2;                  /*!<  ADC Config Register2,                                 Address offset: 0x18 */
  __IO uint32_t SMTR;                   /*!<  ADC Sampling Time Register,                           Address offset: 0x1C */
  __IO uint32_t CHER;                   /*!<  ADC Channel Enable Register,                          Address offset: 0x20 */
  __IO uint32_t DCR;                    /*!< Sampling Register,                                     Address offset: 0x24 */
  __I  uint32_t DR;                     /*!<  ADC Data Register,                                    Address offset: 0x28 */
  __IO uint32_t HLTR;                   /*!<  ADC analog watchdog Threshold Register,               Address offset: 0x2C */
}ADC_Type;


/* ================================================================================ */
/* ================                       PGL                      ================ */
/* ================================================================================ */

typedef struct
{
  __IO uint32_t CR;                     /*!<  ,                                                     Address offset: 0x00 */
  __IO uint32_t CFGR0;                  /*!<  ,                                                     Address offset: 0x04 */
  __IO uint32_t CFGR1;                  /*!<  ,                                                     Address offset: 0x08 */
  __IO uint32_t CFGR2;                  /*!<  ,                                                     Address offset: 0x0C */
  __IO uint32_t CFGR3;                  /*!<  ,                                                     Address offset: 0x10 */
  __IO uint32_t IER;                    /*!<  ,                                                     Address offset: 0x14 */
  __IO uint32_t ISR;                    /*!<  ,                                                     Address offset: 0x18 */
  __IO uint32_t LUT0;                   /*!<  ,                                                     Address offset: 0x1C */
  __IO uint32_t LUT1;                   /*!<  ,                                                     Address offset: 0x20 */
  __IO uint32_t LUT2;                   /*!<  ,                                                     Address offset: 0x24 */
  __IO uint32_t LUT3;                   /*!<  ,                                                     Address offset: 0x28 */
}PGL_Type;


/* ================================================================================ */
/* ================                       TSI                      ================ */
/* ================================================================================ */

typedef struct
{
  __IO uint32_t ISR;                    /*!<  ,                                                     Address offset: 0x00 */
  __IO uint32_t IER;                    /*!<  ,                                                     Address offset: 0x04 */
  __I  uint32_t SSR;                    /*!<  ,                                                     Address offset: 0x08 */
  __IO uint32_t CFGR;                   /*!<  ,                                                     Address offset: 0x0C */
  __IO uint32_t CR;                     /*!<  ,                                                     Address offset: 0x10 */
  __IO uint32_t CHCFGR;                 /*!<  ,                                                     Address offset: 0x14 */
  __I  uint32_t CNTR;                   /*!<  ,                                                     Address offset: 0x18 */
  __IO uint32_t CCR;                    /*!<  ,                                                     Address offset: 0x1C */
  __IO uint32_t DMACR;                  /*!<  ,                                                     Address offset: 0x20 */
  __IO uint32_t CH0CFGR;                /*!<  ,                                                     Address offset: 0x24 */
  __IO uint32_t CH1CFGR;                /*!<  ,                                                     Address offset: 0x28 */
  __IO uint32_t CH2CFGR;                /*!<  ,                                                     Address offset: 0x2C */
  __IO uint32_t CH3CFGR;                /*!<  ,                                                     Address offset: 0x30 */
  __IO uint32_t CH4CFGR;                /*!<  ,                                                     Address offset: 0x34 */
  __IO uint32_t CH5CFGR;                /*!<  ,                                                     Address offset: 0x38 */
  __IO uint32_t CH6CFGR;                /*!<  ,                                                     Address offset: 0x3C */
  __IO uint32_t CH7CFGR;                /*!<  ,                                                     Address offset: 0x40 */
  __IO uint32_t CH8CFGR;                /*!<  ,                                                     Address offset: 0x44 */
  __IO uint32_t CH9CFGR;                /*!<  ,                                                     Address offset: 0x48 */
  __IO uint32_t CH10CFGR;               /*!<  ,                                                     Address offset: 0x4C */
  __IO uint32_t CH11CFGR;               /*!<  ,                                                     Address offset: 0x50 */
  __IO uint32_t CH12CFGR;               /*!<  ,                                                     Address offset: 0x54 */
  __IO uint32_t CH13CFGR;               /*!<  ,                                                     Address offset: 0x58 */
  __IO uint32_t PROXCFGR;               /*!<  ,                                                     Address offset: 0x5C */
  __IO uint32_t IDACTR;                 /*!<  ,                                                     Address offset: 0x60 */
  __IO uint32_t ANACR;                  /*!<  ,                                                     Address offset: 0x64 */
  __IO uint32_t TEST;                   /*!<  ,                                                     Address offset: 0x68 */
  __IO uint32_t ANATEST;                /*!<  ,                                                     Address offset: 0x6C */
}TSI_Type;


/* ================================================================================ */
/* ================                      GPIOx                     ================ */
/* ================================================================================ */

typedef struct
{
  __IO uint32_t INEN;                   /*!<  GPIOx Input Enable Register,                          Address offset: 0x00 */
  __IO uint32_t PUDEN;                  /*!<  GPIOx Pull-Up Pull-Down Enable Register,              Address offset: 0x04 */
  __IO uint32_t ODEN;                   /*!<  GPIOx Open-Drain Enable Register,                     Address offset: 0x08 */
  __IO uint32_t FCR;                    /*!<  GPIOx Function Control Register,                      Address offset: 0x0C */
  __IO uint32_t DO;                     /*!<  GPIOx Data Output Register,                           Address offset: 0x10 */
  __O  uint32_t DSET;                   /*!<  GPIOx Data Set Register,                              Address offset: 0x14 */
  __O  uint32_t DRST;                   /*!<  GPIOx Data Reset Register,                            Address offset: 0x18 */
  __I  uint32_t DIN;                    /*!<  GPIOx Data Input Register,                            Address offset: 0x1C */
  __IO uint32_t DFS;                    /*!<  GPIOx Digital Function Select,                        Address offset: 0x20 */
  __IO uint32_t RSV1;                   /*!<  RESERVED REGISTER,                                    Address offset: 0x24 */
  __IO uint32_t ANEN;                   /*!<  GPIOx Analog channel Enable Register,                 Address offset: 0x28 */
  __IO uint32_t DSR;                    /*!<  GPIOx Driver Strength Register,                       Address offset: 0x2C */
  __IO uint32_t TMUXR;                  /*!<  GPIOC Timer Mux Register,                             Address offset: 0x30 */
}GPIO_Type;


/* ================================================================================ */
/* ================                      GPIO                      ================ */
/* ================================================================================ */

typedef struct
{
  __IO uint32_t EXTISEL0;               /*!<  External Interrupt Input Select Register0,            Address offset: 0x00 */
  __IO uint32_t EXTISEL1;               /*!<  External Interrupt Input Select Register1,            Address offset: 0x04 */
  __IO uint32_t EXTIEDS0;               /*!<  External Interrupt Edge Select and Enable Register0,  Address offset: 0x08 */
  __IO uint32_t EXTIEDS1;               /*!<  External Interrupt Edge Select and Enable Register1,  Address offset: 0x0C */
  __IO uint32_t EXTIDF;                 /*!<  External Interrupt Digital Filter Register,           Address offset: 0x10 */
  __IO uint32_t EXTIISR;                /*!<  External Interrupt and Status Register,               Address offset: 0x14 */
  __I  uint32_t EXTIDI;                 /*!<  External Interrupt Data Input Register,               Address offset: 0x18 */
  __IO uint32_t RSV1[9];                /*!<  RESERVED REGISTER,                                    Address offset: 0x1C */
  __IO uint32_t FOUTSEL;                /*!<  Frequency Output Select Register,                     Address offset: 0x40 */
  __IO uint32_t RSV2[63];               /*!<  RESERVED REGISTER,                                    Address offset: 0x44 */
  __IO uint32_t PINWKEN;                /*!<  Wakeup Enable Register,                               Address offset: 0x140 */
}GPIO_COMMON_Type;


/* ================================================================================ */
/* ================                       SFU                      ================ */
/* ================================================================================ */

typedef struct
{
  __IO uint32_t RAMP_CR;                /*!<  RAM Parity Control Register,                          Address offset: 0x00 */
  __IO uint32_t RAMP_SR;                /*!<  RAM Parity Status Register,                           Address offset: 0x04 */
  __IO uint32_t MAP_CR;                 /*!<  Memory Access Protection Control Register,            Address offset: 0x08 */
  __IO uint32_t MAP_SR;                 /*!<  Memory Access Protection Control Register,            Address offset: 0x0C */
}SFU_Type;


/* ================================================================================ */
/* ================                       DBG                      ================ */
/* ================================================================================ */

typedef struct
{
  __IO uint32_t RSV1;                   /*!<  RESERVED REGISTER,                                    Address offset: 0x00 */
  __IO uint32_t CR;                     /*!<  ,                                                     Address offset: 0x04 */
  __IO uint32_t HDFR;                   /*!<  ,                                                     Address offset: 0x08 */
}DBG_Type;



/* --------------------  End of section using anonymous unions  ------------------- */
#if defined(__CC_ARM)
  #pragma pop
#elif defined(__ICCARM__)
  /* leave anonymous unions enabled */
#elif defined(__GNUC__)
/* anonymous unions are enabled by default */
#elif defined(__TMS470__)
  /* anonymous unions are enabled by default */
#elif defined(__TASKING__)
  #pragma warning restore
#else
  #warning Not supported compiler type
#endif


/* ================================================================================ */
/* ================              CPU memory map                    ================ */
/* ================================================================================ */


/* Peripheral and SRAM base address */

#define FLASH_BASE            ((     uint32_t)0x00000000)
#define SRAM_BASE             ((     uint32_t)0x20000000)
#define PERIPH_BASE           ((     uint32_t)0x40000000)


/* ================================================================================ */
/* ================              Peripheral memory map             ================ */
/* ================================================================================ */

/* Peripheral memory map */

#define FLS_BASE                        (PERIPH_BASE        +0x00001000)
#define PMU_BASE                        (PERIPH_BASE        +0x00002000)
#define VREFP_BASE                      (PERIPH_BASE        +0x00002040)
#define SCU_BASE                        (PERIPH_BASE        +0x00000000)
#define INTMUX_BASE                     (PERIPH_BASE        +0x00016000)
#define RMU_BASE                        (PERIPH_BASE        +0x00002800)
#define IWDT_BASE                       (PERIPH_BASE        +0x00011400)
#define WWDT_BASE                       (PERIPH_BASE        +0x00011800)
#define CMU_BASE                        (PERIPH_BASE        +0x00002400)
#define SVD_BASE                        (PERIPH_BASE        +0x0001A800)
#define AES_BASE                        (PERIPH_BASE        +0x0001B800)
#define RNG_BASE                        (PERIPH_BASE        +0x0001BC00)
#define COMP1_BASE                      (PERIPH_BASE        +0x00019C00)
#define COMP2_BASE                      (PERIPH_BASE        +0x00019C04)
#define COMP_COMMON_BASE                (PERIPH_BASE        +0x00019C0C)
#define DIVAS_BASE                      (PERIPH_BASE        +0x00013000)
#define I2CSMB0_BASE                    (PERIPH_BASE        +0x00012400)
#define I2CSMB1_BASE                    (PERIPH_BASE        +0x00012800)
#define I2C0_BASE                       (PERIPH_BASE        +0x00015000)
#define I2C1_BASE                       (PERIPH_BASE        +0x00015400)
#define I2C2_BASE                       (PERIPH_BASE        +0x00015800)
#define I2C3_BASE                       (PERIPH_BASE        +0x00015C00)
#define UART_COMMON_BASE                (PERIPH_BASE        +0x00017C00)
#define UART0_BASE                      (PERIPH_BASE        +0x00011C00)
#define UART1_BASE                      (PERIPH_BASE        +0x00012000)
#define UART2_BASE                      (PERIPH_BASE        +0x00017400)
#define UART3_BASE                      (PERIPH_BASE        +0x00017800)
#define UART4_BASE                      (PERIPH_BASE        +0x0001A000)
#define UART5_BASE                      (PERIPH_BASE        +0x0001A400)
#define LPUART1_BASE                    (PERIPH_BASE        +0x00010400)
#define SPI0_BASE                       (PERIPH_BASE        +0x00019000)
#define SPI1_BASE                       (PERIPH_BASE        +0x00018C00)
#define SPI2_BASE                       (PERIPH_BASE        +0x00010800)
#define SPI3_BASE                       (PERIPH_BASE        +0x00014000)
#define CAN0_BASE                       (PERIPH_BASE        +0x00019400)
#define CAN1_BASE                       (PERIPH_BASE        +0x00018800)
#define DMA_BASE                        (PERIPH_BASE        +0x00000400)
#define CRC_BASE                        (PERIPH_BASE        +0x00018000)
#define ATIM_BASE                       (PERIPH_BASE        +0x0001B000)
#define TAU_COMMON_BASE                 (PERIPH_BASE        +0x00013C00)
#define TAU0_BASE                       (PERIPH_BASE        +0x00013C10)
#define TAU1_BASE                       (PERIPH_BASE        +0x00013CF0)
#define BSTIM16_BASE                    (PERIPH_BASE        +0x0001B400)
#define LPTIM16_BASE                    (PERIPH_BASE        +0x00013400)
#define RTC_BASE                        (PERIPH_BASE        +0x00011000)
#define LCD_BASE                        (PERIPH_BASE        +0x00010C00)
#define ADC_BASE                        (PERIPH_BASE        +0x0001AC00)
#define PGL_BASE                        (PERIPH_BASE        +0x00013800)
#define TSI_BASE                        (PERIPH_BASE        +0x00010000)
#define GPIOA_BASE                      (PERIPH_BASE        +0x00000C00)
#define GPIOB_BASE                      (PERIPH_BASE        +0x00000C40)
#define GPIOC_BASE                      (PERIPH_BASE        +0x00000C80)
#define GPIOD_BASE                      (PERIPH_BASE        +0x00000CC0)
#define GPIOE_BASE                      (PERIPH_BASE        +0x00000D00)
#define GPIOF_BASE                      (PERIPH_BASE        +0x00000D40)
#define GPIO_BASE                       (PERIPH_BASE        +0x00000DC0)
#define SFU_BASE                        (PERIPH_BASE        +0x00001C00)
#define DBG_BASE                        (PERIPH_BASE        +0x00000000)

/* ================================================================================ */
/* ================             Peripheral declaration             ================ */
/* ================================================================================ */

#define FLASH                           ((FLASH_Type        *) FLS_BASE         )
#define PMU                             ((PMU_Type          *) PMU_BASE         )
#define VREFP                           ((VREFP_Type        *) VREFP_BASE       )
#define SCU                             ((SCU_Type          *) SCU_BASE         )
#define INTMUX                          ((INTMUX_Type       *) INTMUX_BASE      )
#define RMU                             ((RMU_Type          *) RMU_BASE         )
#define IWDT                            ((IWDT_Type         *) IWDT_BASE        )
#define WWDT                            ((WWDT_Type         *) WWDT_BASE        )
#define CMU                             ((CMU_Type          *) CMU_BASE         )
#define SVD                             ((SVD_Type          *) SVD_BASE         )
#define AES                             ((AES_Type          *) AES_BASE         )
#define RNG                             ((RNG_Type          *) RNG_BASE         )
#define COMP1                           ((COMP_Type         *) COMP1_BASE       )
#define COMP2                           ((COMP_Type         *) COMP2_BASE       )
#define COMP                            ((COMP_COMMON_Type  *) COMP_COMMON_BASE )
#define DIVAS                           ((DIVAS_Type        *) DIVAS_BASE       )
#define I2CSMB0                         ((I2CSMB_Type       *) I2CSMB0_BASE     )
#define I2CSMB1                         ((I2CSMB_Type       *) I2CSMB1_BASE     )
#define I2C0                            ((I2C_Type          *) I2C0_BASE        )
#define I2C1                            ((I2C_Type          *) I2C1_BASE        )
#define I2C2                            ((I2C_Type          *) I2C2_BASE        )
#define I2C3                            ((I2C_Type          *) I2C3_BASE        )
#define UART                            ((UART_COMMON_Type  *) UART_COMMON_BASE )
#define UART0                           ((UART_Type         *) UART0_BASE       )
#define UART1                           ((UART_Type         *) UART1_BASE       )
#define UART2                           ((UART_Type         *) UART2_BASE       )
#define UART3                           ((UART_Type         *) UART3_BASE       )
#define UART4                           ((UART_Type         *) UART4_BASE       )
#define UART5                           ((UART_Type         *) UART5_BASE       )
#define LPUART1                         ((LPUART_Type       *) LPUART1_BASE     )
#define SPI0                            ((SPI_Type          *) SPI0_BASE        )
#define SPI1                            ((SPI_Type          *) SPI1_BASE        )
#define SPI2                            ((SPI_Type          *) SPI2_BASE        )
#define SPI3                            ((SPI_Type          *) SPI3_BASE        )
#define CAN0                            ((CAN_Type          *) CAN0_BASE        )
#define CAN1                            ((CAN_Type          *) CAN1_BASE        )
#define DMA                             ((DMA_Type          *) DMA_BASE         )
#define CRC                             ((CRC_Type          *) CRC_BASE         )
#define ATIM                            ((ATIM_Type         *) ATIM_BASE        )
#define TAU                             ((TAU_COMMON_Type   *) TAU_COMMON_BASE  )
#define TAU0                            ((TAU0_Type         *) TAU0_BASE        )
#define TAU1                            ((TAU1_Type         *) TAU1_BASE        )
#define BSTIM16                         ((BSTIM16_Type      *) BSTIM16_BASE     )
#define LPTIM16                         ((LPTIM16_Type      *) LPTIM16_BASE     )
#define RTC                             ((RTC_Type          *) RTC_BASE         )
#define LCD                             ((LCD_Type          *) LCD_BASE         )
#define ADC                             ((ADC_Type          *) ADC_BASE         )
#define PGL                             ((PGL_Type          *) PGL_BASE         )
#define TSI                             ((TSI_Type          *) TSI_BASE         )
#define GPIOA                           ((GPIO_Type         *) GPIOA_BASE       )
#define GPIOB                           ((GPIO_Type         *) GPIOB_BASE       )
#define GPIOC                           ((GPIO_Type         *) GPIOC_BASE       )
#define GPIOD                           ((GPIO_Type         *) GPIOD_BASE       )
#define GPIOE                           ((GPIO_Type         *) GPIOE_BASE       )
#define GPIOF                           ((GPIO_Type         *) GPIOF_BASE       )
#define GPIO                            ((GPIO_COMMON_Type  *) GPIO_BASE        )
#define SFU                             ((SFU_Type          *) SFU_BASE         )
#define DBG                             ((DBG_Type          *) DBG_BASE         )

/* ================================================================================ */
/* ================             Peripheral include                 ================ */
/* ================================================================================ */

/** @} */ /* End of group Device_Peripheral_Registers */
/** @} */ /* End of group FM33FR0XX */
/** @} */ /* End of group Keil */

#ifdef __cplusplus
}
#endif

#endif  /* FM33FR0XX_H */

