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#### 14.21.3 RTL SSA Basic Blocks

RTL SSA instructions (see RTL SSA Instructions) are organized into basic blocks, with each block being represented by an `rtl_ssa:bb_info`. There is a one-to-one mapping between these `rtl_ssa:bb_info` structures and the underlying CFG `basic_block` structures (see Basic Blocks).

If a CFG basic block bb contains an RTL instruction insn, the RTL SSA represenation of bb also contains an RTL SSA representation of insn 5. Within RTL SSA, these instructions are referred to as “real” instructions. These real instructions fall into two groups: debug instructions and nondebug instructions. Only nondebug instructions should affect code generation decisions.

In addition, each RTL SSA basic block has two “artificial” instructions: a “head” instruction that comes before all the real instructions and an “end” instruction that comes after all real instructions. These instructions exist to represent things that are conceptually defined or used at the start and end of a basic block. The instructions always exist, even if they do not currently do anything.

Like instructions, these blocks are chained together in a reverse postorder. This list includes the entry block (which always comes first) and the exit block (which always comes last).

RTL SSA basic blocks are chained together into “extended basic blocks” (EBBs), represented by an `rtl_ssa::ebb_info`. Extended basic blocks contain one or more basic blocks. They have the property that if a block bby comes immediately after a block bbx in an EBB, then bby can only be reached by bbx; in other words, bbx is the sole predecessor of bby.

Each extended basic block starts with an artificial “phi node” instruction. This instruction defines all phi nodes for the EBB (see RTL SSA Phi Nodes). (Individual blocks in an EBB do not need phi nodes because their live values can only come from one source.)

The contents of a function are therefore represented using a four-level hierarchy:

- functions (`rtl_ssa::function_info`), which contain …
- extended basic blocks (`rtl_ssa::ebb_info`), which contain …
- basic blocks (`rtl_ssa::bb_info`), which contain …
- instructions (`rtl_ssa::insn_info`)

In dumps, a basic block is identified as `bbn`, where n is the index of the associated CFG `basic_block` structure. An EBB is in turn identified by the index of its first block. For example, an EBB that contains ‘`bb10`’, `bb5`, `bb6` and `bb9` is identified as ebb10.

#### Footnotes

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Note that this excludes non-instruction things like `note`s and `barrier`s that also appear in the chain of RTL instructions.

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